//date:6/2
//author:李嘉霖
module mac (
input clk, 
input rst_n,
input en, first_data, last_data,
input signed [7:0] image_i,
input signed [7:0] weight_i,
output reg signed [15:0] q,
output reg q_en
);

reg signed [15:0] sum;

always@(posedge clk)
begin
    if({rst_n,en}==2'b00) 
        begin
            sum <= 0;
            q_en <= 1'b0;
        end
    else if({rst_n,en}==2'b01)
        begin
            sum <= 0;
            q_en <= 1'b0;
        end
    else if({rst_n,en}==2'b10)
        begin
            sum <= 0;
            q_en <= 1'b0;
        end
    else if({rst_n,en}==2'b11)
        begin
            if({first_data,last_data}==2'b10)
                begin
                    sum <= image_i * weight_i;
                    q_en <= 1'b0;
                end
            else if({first_data,last_data}==2'b00)
                begin
                    sum <= sum + image_i * weight_i;
                    q_en <= 1'b0;
                end
            else if({first_data,last_data}==2'b01)
                begin
                    sum = sum + image_i * weight_i;
                    q = sum;
                    sum = 0;
                    q_en = 1'b1;
                end
            else
                begin
                    sum <= 0;
                    q_en <= 1'b0;
                end
        end
end

/*always@(posedge q_en)
begin
    q = sum;
    sum = 0;
end
always@(negedge q_en)
begin
    q = 0;
end*/

endmodule